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Optimal Hardware Pattern Generation for Functional BIST

title Optimal Hardware Pattern Generation for Functional BIST
creator Cataldo, Silvia
Chiusano, Silvia
Prinetto, Paolo
Wunderlich, Hans-Joachim
date 2000-03
language eng
identifier  http://www.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2000-46&engl=1
ISBN: ISBN: 0-7695-0537-6
ISBN: DOI: 10.1109/DATE.2000.840286
description Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses the computation of optimal seeds for an arbitrary sequential module to be used as hardware test pattern generator. Up to now, only linear feedback shift registers and accumulator based structures have been used for deterministic test pattern generation by reseeding. In this paper, a method is proposed which can be applied to general finite state machines. Nevertheless the method is absolutely general, for sake of comparison with previous approaches, in this paper an accumulator based unit is assumed as pattern generator module. Experiments prove the effectiveness of the approach which outperforms previous results for accumulators, in terms of test size and test time, without sacrifying the fault detection capability.
publisher Institute of Electrical and Electronics Engineers
type Text
Article in Proceedings
source In: Proceedings of the 3rd Conference on Design and Test in Europe (DATE), Paris, France, March 27-30, 2000, pp. 292-297
contributor Rechnerarchitektur (IFI)
subject Reliability, Testing, and Fault-Tolerance (CR B.8.1)